A metal-oxide semiconductor (MOS) field-effect transistor (MOSFET) can be operated as a switch in the transistor's triode or linear region. Such a switch can be conceptualized as a resistor whose value is controlled by the transistor gate-source voltage. When the gate voltage causes the switch to be closed, the resistance may be only a few ohms, which effectively presents a closed circuit. When the gate voltage causes the switch to be open, the resistance is so high as to effectively present an open circuit. However, in reality there are parasitic capacitances in the transistor. In some instances, the resistance can be non-linear, where the resistance becomes dependent upon the transistor source terminal voltage due to the charging times of capacitances. For example, a MOS transistor-based switch in a mixer of the type used in some wireless telephone handset circuits can be driven into non-linear operation by the larger voltage signals that are commonly employed in direct-conversion radio receivers and transmitters to provide noise immunity. Non-linear operation can result in intermodulation distortion that hampers receiver or transmitter performance.
An exemplary quadrature mixer 10 having a transmission gate structure to promote linearity is illustrated in FIG. 1. Mixer 10 has sections that can be referred to for convenience herein as switches 12, 13, 14, 15, 16, 17, 18 and 19. The term “switch” as used herein refers to any circuitry that performs a switching function and can include one or more individual switching elements such as transistors or groups of transistors. Switch 12 mixes a positive in-phase input signal (Ip, labeled in FIG. 1 as “I_P” for readability) with a local oscillator (LO) signal and a frequency-doubled local oscillator (2LO) signal. Switch 14 mixes a negative in-phase input signal (Im, labeled in FIG. 1 as “I_M” for readability) with the LO and 2LO signals. Switch 16 mixes a positive quadrature input signal (Qp, labeled in FIG. 1 as “Q P” for readability) with the LO and 2LO signals. Switch 18 mixes a negative quadrature (Qm, labeled in FIG. 1 as “Q_M” for readability) input signal with the LO and 2LO signals. As known in the art, timing circuitry (not shown) causes each of these input signals to be asserted sequentially while the others are de-asserted: Ip, Qp, Im, Qm, Ip, Qp . . . . Accordingly, the mixer output signals OUT__P and OUT__M sequentially represent the result of mixing Ip, Qp, Im, Qm, etc., with the LO and 2LO signals. The architecture of mixer 10 is sometimes referred to as “L0-2L0.”
Each of switches 12, 13, 14, 15, 16, 17, 18 and 19 includes at least one transmission gate comprising an n-channel MOS (nMOS) transistor and a p-channel MOS (pMOS) transistor in parallel with each other. Switch 12 includes transmission gate 20, comprising nMOS transistor 22 and pMOS transistor 24, and transmission gate 32, comprising nMOS transistor 34 and pMOS transistor 36. Switch 13 includes transmission gate 26, comprising nMOS transistor 28 and pMOS transistor 30, and transmission gate 50, comprising nMOS transistor 52 and pMOS transistor 54. Switch 14 includes transmission gate 38, comprising nMOS transistor 40 and pMOS transistor 42, and transmission gate 32, comprising nMOS transistor 34 and pMOS transistor 36. Switch 15 includes transmission gate 44, comprising nMOS transistor 46 and pMOS transistor 48, and transmission gate 50, comprising nMOS transistor 52 and pMOS transistor 54. Switch 16 includes transmission gate 56, comprising nMOS transistor 58 and pMOS transistor 60, and transmission gate 68, comprising nMOS transistor 70 and pMOS transistor 72. Switch 17 includes transmission gate 62, comprising nMOS transistor 64 and pMOS transistor 66, and transmission gate 86, comprising nMOS transistor 88 and pMOS transistor 90. Switch 18 includes transmission gate 74, comprising nMOS transistor 76 and pMOS transistor 78, and transmission gate 68, comprising nMOS transistor 70 and pMOS transistor 72. Switch 19 includes transmission gate 80, comprising nMOS transistor 82 and pMOS transistor 84, and transmission gate 86, comprising nMOS transistor 88 and pMOS transistor 90. Note that some transmission gates are included in two switches.
The LO signals are coupled to the gate terminals of transistors 22, 24, 28, 30, 40, 42, 46, 48, 58, 60, 64, 66, 76, 78, 82 and 84, while the 2LO signals are coupled to the gate terminals of transistors 34, 36, 52, 54, 70, 72, 88 and 90. The LO signals are coupled to the gate terminals via capacitors 92, although only one such capacitor 92 is shown for purposes of clarity. (The ellipsis symbol (“. . .”) is used herein to indicate circuitry or connections not shown.) Similarly, the 2LO signals are coupled to the gate terminals via capacitors 93, although only one such capacitor 93 is shown for purposes of clarity. The gate terminals are also coupled to a fixed or constant bias voltage, V_BIAS, via resistors 94, although only one such resistor 94 is shown for purposes of clarity. It can be noted that the above-referenced gate terminals are coupled to various time-shifted versions of the LO and 2LO signals, which can be referred to as LO_I_P, L0_I_M, LO_Q_P, L0_Q_M, 2LO__P and 2L0_M, although in FIG. 1 all such signals are simply labeled either “LO” or “2LO” (i.e., without differentiation) for purposes of clarity.
Including the pMOS transistors promotes linear switch operation. It is known that by sizing the pMOS transistor on the order of three times larger than the nMOS transistor in each transmission gate, the transmission gate can be made to switch substantially linearly (i.e., the transmission gate resistance is made linear) over the range of voltages commonly employed in mixers used in some direct-conversion radio receivers and transmitters. If the pMOS transistors were not present (i.e., only nMOS transistors were present) or were not sized in this manner, and if no other measures were taken to promote linear operation, the switching would be susceptible to non-linear operation due to parasitic capacitances between switches. In non-linear operation, the transition time from one output signal, Ip, Qp, Im, Qm, etc., to the next in the sequence depends upon the voltages of those signals, due to the charging times of the capacitances. That is, the previous voltage state of the parasitic capacitance introduces a memory effect, which is the source of the non-linearity.
Other techniques for improving switch linearity have been described, such as feeding back the signal at the source terminal of the switching transistor to the gate of an nMOS transistor to cause the gate voltage to follow the source voltage, such that the gate-to-source voltage is nearly constant. Such a “feedback” or “bootstrapping” technique may not provide good results in a passive mixer of the type used in some direct conversion radio receivers and transmitters because the source and drain terminal voltages of symmetric CMOS transistors interchange, i.e., switch, with one another during mixer operation.